FIG. 1 schematically illustrates a traditional sensing circuit with an eFuse unit cell. As shown, the circuit in FIG. 1 includes eFuse unit cell 101 connected to sensing circuit 103. eFuse unit cell 101 includes fuse 105 having one end coupled to a source (e.g., FSOURCE) and another end coupled to program transistor 107. While program transistor 107 is activated (e.g., based on inputs, FU_ROW_PG and FU_CLM_PG, to AND gate 109), a large current from FSOURCE may go through eFuse unit cell 101, causing fuse 105 to become blown. To detect the fuse state (e.g., blown, unblown, etc.) of fuse 105, eFuse unit cell 101 includes reference resistor 111 along with transistors 113 and 115 that are connected to sensing circuit 103.
Sensing circuit 103 includes inverters 117a through 117e and NAND gate 119. As depicted, the various outputs (e.g., SSW_N, SRES_P, SET_P11, SET_N11, SET_P22, SET_N22, etc.) of inverters 117a through 117e and NAND gate 119 act as switches for transistors within sensing circuit 103. For example, when transistors 113 and 115 are enabled (e.g., by FU_ROW_RD), and PRCHG is high, the two pre-charge paths from a power rail (e.g., VDD) to a ground rail (e.g., during such a situation, FSOURCE may be coupled to a ground rail) may be activated. The first path may, for instance, include transistor 121, transistor 123, transistor 113, and fuse 105, and the second path may include transistor 125, transistor 127, transistor 115, and reference resistor 111. The resistance of reference resistor 111 is greater than the resistance of unblown fuse 105, and less than that of blown fuse 105. If fuse 105 is unblown, the voltage at the node between transistors 129 and 131 (e.g., node A) will be less than the voltage at the node between transistors 133 and 135 (e.g., node B); if fuse 105 is blown, the voltage at the node between transistors 129 and 131 (e.g., node A) will be greater than the voltage at the node between transistors 133 and 135 (e.g., node B). Transistors 129, 131, 133, and 135 are two back-to-back inverter pairs that make up a latch (e.g., that is coupled to transistors 137 and 139). When SENSE is enabled, the initial voltage difference between nodes A and B will cause the latch to fix to a certain state after becoming balanced, and provide a DOUT signal (e.g., through inverter 141, pass-gate 143, and inverters 145, 147, and 149.
In order for the latch to provide an accurate fuse state of eFuse unit cell 101, the initial voltage difference between nodes A and B typically must be large enough for detection. However, because of variations of process, voltage, temperature, etc., the sense margin is difficult to tune for each process. Although the sense margin may be increased to make up for such variations, an increase in the sense margin will result in an increase in the current for the PRCHG and SENSE inputs, causing power consumption of sensing circuit 103 to be very high. In addition, the back-to-back inverter latch sense scheme and the two-stage sense procedure requiring a pre-charge before reading out data utilizes additional pins (e.g., PRCHG pins) and results in a very long read cycle time.
A need therefore exists for a more efficient and effective fuse sensing circuit that consumes less power, does not require additional pre-charge pins, avoids unnecessary pre-charging, and has faster read cycle speeds, and enabling methodology.